There has been proposed what is called a three-level converter that obtains three levels of DC potential from a three-phase rectifier circuit. The three-level converter is illustrated, for example, in Specification of European Patent Application Publication No. 0660498, Japanese Patent Application Laid-Open No. 9-182441 (1997) and Japanese Patent Application Laid-Open No. 2002-142458 and J. W. Kolar, U. Drofenik, F. C. Zach, “DC link voltage balancing of a three-phase/switch/level PWM (VIENNA) rectifier by modified hysteresis input current control”, Proc. of Power Conversion Conference 1995, 1995, pp. 443-465 and Zhao, Y., Y. Li, T. A. Lipo, “Force Commutated Three-Level Boost Type Rectifier”, IEEE-IAS Conference Record, October 1993, vol. II, 1993, pp. 771-777 to be described below.
FIG. 16 is a circuit diagram of a three-level converter presented in FIG. 4 of Specification of European Patent Application Publication No. 0660498. A three-phase voltage is applied to first ends of respective inductors 8, 9 and 10 that are a set of three reactors. The inductors 8, 9 and 10 have second ends, respectively, connected through feeders 11, 12 and 13 to terminals 14, 15 and 16. The terminals 14, 15 and 16 function as input ends of a power supply three-phase diode bridge 17 composed of diodes 18, 19, 20, 24, 25 and 26. The power supply three-phase diode bridge 17 has outputs connected through feeders 21 and 27 to capacitors 6 and 7, respectively.
The terminals 14, 15 and 16 are connected through bidirectional switches 30, 31 and 32, respectively, to a neutral point 33. A switching element 61 in the bidirectional switch 30 has a collector 77 and an emitter 78. A switching element 61 in the directional switch 31 has a collector 79 and an emitter 80. A switching element 61 in the bidirectional switch 32 has a collector 81 and an emitter 82.
The conduction of any one of the switching elements 61 causes the potential at any one of the terminals 14, 15 and 16 to be applied through a feeder 34 to an intermediate point 35 between the series-connected capacitors 6 and 7. A DC voltage is developed at output ends 23 and 29 by the function of the three-phase diode bridge 17.
FIG. 17 is a circuit diagram of a three-level converter presented in FIG. 1 of Zhao, Y., Y. Li, T. A. Lipo, “Force Commutated Three-Level Boost Type Rectifier”, IEEE-IAS Conference Record, October 1993, vol. II, 1993, pp. 771-777. A similar circuit is also presented in FIG. 4 of Japanese Patent Application Laid-Open No. 2002-142458. In the circuit, three phase currents Ia, Ib and Ic flow from the side of three phase voltages Va, Vb and Vc.
The current Ia flows either through a diode D12 and a switch S11 or through a diode D13 and a switch S12 to become a current In flowing to a neutral point n. Otherwise the current Ia flows either through diodes D11 and D12 or through diodes D13 and D14 to the capacitors. The current Ib flows either through a diode D22 and a switch S21 or through a diode D23 and a switch S22 to become the current In. Otherwise the current Ib flows either through diodes D21 and D22 or through diodes D23 and D24 to the capacitors. The current Ic flows either through a diode D32 and a switch S31 or through a diode D33 and a switch S32 to become the current In. Otherwise the current Ic flows either through diodes D31 and D32 or through diodes D33 and D34 to the capacitors.
In this manner, the switches S11, S22 and S31 and the switches S12, S22 and S32 are separately responsible for breakdown voltage during the time interval that the phase voltages are positive and during the time interval that the phase voltages are negative, and charge the two capacitors to a voltage of Vd/2.
Thus, it is sufficient for the breakdown voltage of the switches S11 to S32 to be approximately one-half that of the switching element 61 in the circuit shown in FIG. 16. However, the number of switching elements in the circuit shown in FIG. 17 doubles the number of switching elements in the circuit shown in FIG. 16.
FIG. 18 is a circuit diagram of a three-level converter presented in FIG. 1 of Japanese Patent Application Laid-Open No. 9-182441 (1997). A feeder 48 is connected through feeders 37 and 38 to the output ends 23 and 29. Together with a feeder 47 connected to the intermediate point 35, the feeder 48 is given to a control unit 40, whereby the measurement values of output voltages are provided to the control unit 40. Phase voltages from a three-phase power supply 5 (phase power supplies 2, 3 and 4) are provided through feeders 44 to 46 (coupled to each other into the form of a three-phase feeder 42) to the control unit 40. An external control signal 41 is separately provided to the control unit 40.
A similar circuit is presented in FIG. 1(a) of J. W. Kolar, U. Drofenik, F. C. Zach, “DC link voltage balancing of a three-phase/switch/level PWM (VIENNA) rectifier by modified hysteresis input current control”, Proc. of Power Conversion Conference 1995, 1995, pp. 443-465 and in FIG. 2 of Japanese Patent Application Laid-Open No. 9-182441 (1997). In this circuit, it is sufficient for the breakdown voltage required for switching elements to be approximately one-half that in the circuit shown in FIG. 16, and the number of switching elements in this circuit does not increase.
Japanese Patent No. 2754519 and Japanese Patent Application Laid-Open No. 2006-115609 and Fumitoshi Ichikawa, and five others, “A Control Scheme of Power Line Compensator with Multiple Function for Maintaining Power Quality”, the Institute of Electrical Engineers of Japan (IEEJ), The Papers of Technical Meeting on Semiconductor Power Converter, SPC-96-127, Keijiroo Sakai, and three others, “Control Methods for Reduction of DC Link Capacitor and Restarting at Instantaneous Power Failure in PWM Converter” the Institute of Electrical Engineers of Japan (IEEJ), Academic Journal D, Vol. 112, No. 1, Heisei 4 (1992) and Compiled by the Institute of Electrical Engineers of Japan (IEEJ), Semiconductor Power Conversion System Investigation Expert Committee, “Power Electronics Circuit”, Ohmsha, Ltd., pp. 176-177, Nov. Heisei 12 (2000) are listed as other documents associated with the present application.